Much of cellXica’s technology is based on Software Defined Radios (SDR). There’s a good history on Wikipedia, so I won’t repeat that here, but I thought I’d share personal perspectives on the subject, having been involved in it on and off since the mid-1980s.
When I graduated in 1984, I joined the Avionics Research Laboratory at the GEC-Marconi Research Centre. At that time our colleagues in the Communications Research Laboratory were developing a bandpass delta sigma ADC for use in a HF receiver. This made use of a single bit convertor in a second-order noise shaping loop with implicit mixing to complex baseband achieved though sub-sampling. One of our projects was to extend the bandwidth to make it suitable for VHF communications by using a 4-bit convertor in the noise shaping loop rather than the comparator used for HF. Associated with this was a second project to implement the signal processing required for processing the output of such a convertor. The front-end signal processing was performed using hardware based on Sony’s SPECL, such as discrete 4-bit ALU, and often required entire PCBs to support a single function, such as a decimating filter. The baseband processing, such as demodulation was implemented in early versions of Motorola’s 56000 DSP family, which had the advantage of 24-bit data words and a 56-bit accumulator, but with clock speeds in the region of 20MHz meant that channel bandwidths were limited to those in the audio region.
The ADC technology was used in an HF radar system and in some test equipment. The digital demodulation work was deployed in the Terrestrial Flight Telephone System (TFTS), a 1990s cellular communications system for passenger aircraft that made use of a network of ground stations. As an example of the advantages of the software receiver implementation, the TFTS hardware was reused in the prototype of the VDL Mode 3 air traffic control radio at the end of the 1990s. The initial prototype made use of five Motorola 56002 based boards clocked at 20MHz and was later replaced by a single Motorola 56300 board clocked at 80MHz, demonstrating the simplification that can be achieved as technology advances.
When programmable DSPs, such as Texas Instruments’ TMS32010 and Motorola’s 56000 were introduced in the early 1980s their key feature was a single cycle MAC. They were programmed in assembler, which was fine for implementing digital signal processing algorithms and for the simple control required for such applications. However, a separate microprocessor was usually employed to support higher level control functions, such as the communications system protocol stack. In the early 2000s new devices began to appear that whilst retaining some of the features of the older DSPs, in particular single cycle multipliers, also had a more general programming model allowing control software to be implemented in C. I was at TTPCom at this time working on S for GSM handsets. Our architecture had three main parts, a radio and associated data convertors, a DSP supported by associated function-specific accelerators to support the signal and data processing aspects of the physical layer and a microcontroller to support the rest of the protocol stack and applications. We ported our physical layer software and protocol stack to run on Starcore’s SC1200 core, the entire system being programmed in C.
Whilst advances in DSP cores offered one driver for changes in SDR implementations another was the development of FPGAs with every increasing programmable logic, memory and hardened functionality. When I joined Airvana in 2007 we were developing UMTS femtocells based on Xilinx Spartan 3 and later Spartan 6 FPGAs to support the computationally intensive physical layer, a discrete microcontroller to support the protocol stack and an RFIC from Analog Devices. The FPGAs included sufficient programmable logic and multiplication units to implement a fairly efficient UMTS physical layer, including support for HSDPA and HSUPA.
In 2010 we combined knowledge gained at Airvana with the latest FPGA and RFIC parts from Xilinx and Analog Devices respectively to start developing the SC5 platform. From the outset the SC5 was intended to support a range of applications, and specifically GSM, UMTS and LTE base stations. In particular it made use of Xilinx’s Zynq FPGAs which in addition to more programmable logic, memory and multipliers than the Spartan parts, also included a pair of hardened ARM Cortex A9 cores. This relieved us of the need to include a separate processor on the circuit board and also allowed a closer coupling between the processors and programmable logic to a give more efficient processing system.
Subsequent advances in the offerings from companies such as Xilinx and Analog Devices have given rise to further opportunities for the implementation of SDRs that we are exploiting in the SC7 platform.
Before closing it is worth a few words on the elephant in the room. Whilst advances in technology have given rise to ever greater processing capacity, sampling rate and dynamic range, there is still the need to process the signal in the analogue domain. Whilst there are some promising approaches to configurable frontends at present a large amount of the board area is taken up with banks of switchable filters.
 “Software-defined radio”, Wikipedia, 24th November 2020.
(Please note, the two sources below require an account to access them, but we’ve included the links in case you would like to dig more deeply:)
 “The application of software radio techniques for airborne passenger telephony and future ATC communication systems”, G.E. Matich, C.D. Reynolds, F.J. Lazare, IEE Colloquium on Air-To-Ground Communications, IET, 1997.
 “Implementing a single-processor cellular modem on an SC1000-family core”, S. Angioni and F. Lazare, Proceedings of 2004 International Symposium on System-on-Chip, IEEE, 2004.